An error correcting decoder is typically implemented, e.g., in a network system, to reduce communication errors. One type of an error correcting decoder is an iterative error correcting decoder. Iterative error correcting decoders typically use a large-scale parallel network of nodes performing soft probability calculation. These nodes exchange probability information of a received data block among one another. After a certain number of iterations within an iterative decoder structure, individual noisy information in a data block (or word) is transformed into an estimate of the word as a whole. Examples of iterative decoders are the low density parity check (LDPC) decoders, Hamming decoders, Reed-Solomon decoders, Turbo decoders, and the like.
The structure of an iterative error correcting decoder can be represented graphically by a factor graph. Factor graphs are the graphical representation of the linear space of codewords (e.g., LDPC codewords). A factor graph consists of nodes and edges, where the edges are simply the wire connections between the nodes, while a node represents a function of its inputs. For example, in a low density parity check (LDPC) factor graph, there are two types of nodes representing two distinct functions—i.e., “equality constraint” nodes and “parity check” nodes. According to the IEEE 802.3ae (10GBASE-T) standard, the proposed LDPC decoder consists of (2048) equality constraint nodes and (384) parity check nodes. Each equality constraint node has (6) bidirectional connections to corresponding parity constraint nodes and each parity check node has a total of (32) bidirectional connections to corresponding equality constraint nodes. This results in a factor graph with a network matrix of (12,228) connections. The probabilities associated with received bit values iterate between these two node functions to finally resolve the most probable value of each data bit.
In an analog implementation of an LDPC decoder, the two node functions—i.e., the equality constraint function and the parity check function—are typically implemented using basic function blocks composed of Gilbert multipliers that are operated in the subthreshold region. The Gilbert multipliers in each node has corresponding output connections tied in such a way to represent the specific basic function for that node. FIG. 1 illustrates a conventional Gilbert basic function block (or cell) 100, including (3) Gilbert multipliers 102 and (3) bidirectional connections 104. Each Gilbert multiplier 102 is a 2-input Gilbert multiplier, and each bidirectional connection 104 interacts with two other bit probabilities. FIGS. 2A and 2B show block diagrams of a conventional equality constraint function 200 and a conventional parity check function 202 of an LDPC decoder, in which each function includes a plurality of Gilbert basic function blocks. Accordingly, in one implementation of a conventional analog LDPC decoder, the equality constraint function and parity check function will have at least [2048*(6−2)*3]+[384*(32−2)*3]˜59,000 Gilbert multipliers. The large number of Gilbert multipliers affects the size and the power of the LDPC decoder.
An important feature of a digital LDPC decoder is the number of iterations that the iterative decoder can perform on an input codeword in a given amount of time as it relates to the bit error rate (BER) of the iterative decoder. In an analog LDPC decoder, received bit values are decoded through a diffusion process, and the amount of time for a signal (e.g., a received bit value) to go (or diffuse) through a predetermined number of equality constraint nodes and parity check nodes can be measured. For example, the parity check function 202 shown in FIG. 2 has a worst case delay of 30 cells. This large delay can be a serious bottleneck in terms of performance, which may require significantly increasing the power (per cell) to handle such a bottleneck. A proposed design to reduce the delay is to implement the Gilbert basic function blocks in a star topology as shown in FIGS. 3A and 3B. FIGS. 3A and 3B show an equality constraint function 300 and a parity check function 302 each implemented in a star topology. With respect to the equality constraint function 300, the star topology reduces the maximum delay between the farthest connection to (3) cells as indicated by path 304. Similarly, with respect to the parity check function 302, the star topology reduces the maximum delay between the farthest connection to (8) cells as indicated by path 306, which is a significant advantage over the (30) cell delay corresponding to the (linear) topology of the parity check function 202 (FIGS. 2A and 2B).
Conventionally, the equality constraint function 300 and the parity check function 302 each typically include a plurality of 2-input Gilbert multipliers, in which each 2-input Gilbert multiplier is followed by a current mirror output stage. For example, FIG. 4 illustrates a circuit diagram of a conventional (differential) 2-input Gilbert multiplier 400 that can be implemented within a parity function block. The 2-input Gilbert multiplier 400 includes an input stage 402 and an output current mirror stage 404. The output current mirror stage 404 is typically implemented at the output of a Gilbert multiplier to ensure connection compatibility among all the Gilbert cells. For example, in the circuit diagram of FIG. 4, as long as all of the output currents (e.g., Xop, Xon) are supplied by PMOS devices and all of the inputs (e.g., Xp1, Xp2, Xn1, Xn2) are NMOS current mirrors, a circuit designer can comfortably connect Gilbert cells together. However, the problem with conventional Gilbert cells with output current mirror stages is the extra propagation delay associated with current mirroring that effectively doubles the overall delay of the cell. Cell delay minimization is critical in high speed application, for example, an analog LDPC decoder requires a minimum amount of diffusion time (or the number of iterations in the digital counterpart) to deliver a target BER performance.